The increasing demand of Active Power Factor Devices (APFD) is driven by the concern for the quality of the power line supplies. Injection of high harmonics into the power line is well-known to cause many problems. Among these are the lower efficiency of power transmission, possible interference to other units connected to the power line, and distortion of the line voltage shape that is undesirable. In addition to resolve these issues, APFD offers another advantage to increase the power level that can be drawn from the power line.
One of the main contributors of Total Harmonic Distortion (THD) in Active Power Factor Correction System (APFCS) is the so-called “Crossover Distortion”. The root cause of the Crossover Distortion is due to the residual voltage across the capacitor 1C1 after the bridge rectifier (refer to FIG. 1). This residual voltage blocks the current flow from bridge rectifier as long as the absolute AC line voltage lower than the residual voltage plus the bridge diode 1BD1 on-forward threshold voltage. During this blocking period, APFCS is equivalent to non power factor correction system. The magnitude of the residual voltage is depend on the capacitance of the total parasitic capacitor at power switch 1NMOS drain node 106 (refer to FIG. 1), inductance of the boost inductor 121, AC line voltage and output loading 1RL (refer to the U.S. Pat. No. 6,946,819).
FIG. 1 shows the prior art of the Active Power Factor Correction system for minimizing the Crossover Distortion (refer to the U.S. Pat. No. 6,946,819). Controller 120 receives feedback signals through the various lines 104, 111, 109, 105. Signal 104 is a rectified line voltage derived from a potential divider comprised of resistors 1R1 and 1R2, and whose shape is used as the Reference for the desired shape of the input current. Signal 111 is the sum of boost inductor current sense signal 112 and 108 from Crossover Distortion Reducer (CDR). The signal 112 serves to sense current flow through boost inductor 121 by sensing the voltage drop across the resistor R8. Negative voltage at node 108 generated from CDR which comprises Diode 1D2 and capacitor 1C4 is proportional to the rectified main voltage and the turn ratio of the auxiliary winding of the boost inductor 121. 109 represents a divided down boosted output signal at node 113 from the potential divider consisting of the resistors 1R9 and 1R10. Signal 105 obtained with an auxiliary winding on the boost inductor 121 serves to monitor the zero voltage crossing the boost inductor 121. Controller 120 is then based on these feedback signals to generate output signal at node 110 which define the on-off period of the power switch 1NMOS. Capacitor 1Cdrain is the equivalent parasitic capacitor connected between the node 106 and ground.
A detail block diagram of Controller 120 (FIG. 1) which is designed to maintain the output voltage at node 113 (FIG. 2) constant by feedback control is shown in FIG. 2. It is consist of an Error Amplifier 201 (FIG. 2), Multiplier 202 (FIG. 2), Comparator 203 (FIG. 2), Zero Crossing Detector (ZCD) 204 (FIG. 2), RS Flip-Flop Register 205 (FIG. 2) and Gate Driver 206 (FIG. 2). The Error Amplifier receives signal from node 109 or Pin 1 (FIG. 2) which is compared with internal set reference voltage, for example 2.5V, to generate an error signal at node 107 or Pin 2 (FIG. 2). The Multiplier 202 serves to multiply the error signal with the divided-down rectified signal at node 104 or Pin 3 (FIG. 2) and to produce a rectified sinusoidal reference signal 2Cr. Comparator 203 (FIG. 2) compares the rectified sinusoidal reference signal 2Cr with signal at node 111 or Pin 4 (FIG. 2) from the CDR to create a logic signal for power switch 1NMOS off control. Signal from node 105 or Pin 5 (FIG. 2) is monitored by Zero Crossing Detector 204 (FIG. 2). At the time when a positive to negative voltage event or so-called “zero crossing” occurs, a logic high signal is generated from Zero Crossing Detector 204 (FIG. 2) to set RS Flip-Flop Register 205 (FIG. 2) that turns to switch on power switch 1NMOS. The boost inductor current and its sense signal voltage at node 111 or Pin 4 (FIG. 2) starts to rise at the time of the power switch 1NMOS on. When the sense signal voltage rises up to equal to the rectified sinusoidal reference signal 2Cr, a reset signal is produced from Comparator 203 (FIG. 2) to reset the RS Flip-Flop Register 205 (FIG. 2) that turns to switch off the power switch 1NMOS. The power switch 1NMOS stays off until next “zero crossing” event and the switch on-off cycle starts over again.
The main concept behind this prior art implementation is to fully discharge capacitor 1C1 at zero crossing of AC line voltage. This can be done by artificially increasing the on-time of the power switch 1NMOS with a negative offset on the current sense input pin 4 of controller 120 at node 111. The negative offset voltage is introduced by CDR and its operation principle is described below:
During the on-time period of power switch 1NMOS, voltage across the auxiliary coil 120 is negative that forward bias diode 1D2 to charge the capacitor 1C4. A negative voltage which is proportional to RMS value of line voltage and the turn ratio of the auxiliary coil 121 is maintained by capacitor 1C4. This negative voltage turns to extend the power switch 1NMOS switching on-time through a potential divider consisting of 1R6 and 1R5, which generates a control signal at node 111, and presents to controller 120 pin 4.
A major drawback of the prior art design is the need of manual adjustment on the resistance value of 1R6 to find the optimum solution. The required offset voltage generated from CDR for THD optimization is output load, AC line voltage and parasitic capacitor capacitance at node 106 dependence. In other words, this design is only good for certain range of loading and equivalent drain capacitance 1Cdrain at node 106.